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K9S1208V0M-SSB0
Document Title 64M x 8 Bit SmartMediaTM Card Revision History
Revision No
0.0 0.1
SmartMediaTM
History
Initial issue 1. Changed DC characteristics Parameter Operating Current Sequential Read Program Erase Min Typ 10 10 10 Max 20->30 20->30 20->30 mA Unit
Draft Date
Mar. 30th 2001 Apr. 7th 2001
Remark
preliminary Final
2. Added tDBSY parameter 3. Removed Copy-Back program command 4. Changed AC characteristics Parameter ALE to RE Delay ( ID read ) Symbol tAR1 Min 100->10 Max Unit ns
Note : For more detailed features and specifications including FAQ, please refer to Samsung' Flash web site. s http://www.intl.samsungsemi.com/Memory/Flash/datasheets.html The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have any questions, please contact the SAMSUNG branch office near your office.
1
K9S1208V0M-SSB0
64M x 8 Bit SmartMediaTM Card
FEATURES
*Single 2.7V~3.6V Supply *Organization - Memory Cell Array : (64M + 2,048K)bit x 8bit - Data Register : (512 + 16)bit x8bit *Automatic Program and Erase - Page Program : (512 + 16)Byte - Block Erase : (16K + 512)Byte *528-Byte Page Read Operation - Random Access : 12s(Max.) - Serial Page Access : 50ns(Min.) *Fast Write Cycle Time - Program Time : 200s(Typ.) - Block Erase Time : 2ms(Typ.) *Command/Address/Data Multiplexed I/O Port *Hardware Data Protection - Program/Erase Lockout During Power Transitions *Reliable CMOS Floating-Gate Technology - Endurance : 100K Program/Erase Cycles - Data Retention : 10 Years *Command Register Operation *22pad SmartMediaTM (SSFDC) *ID for Copyright Protection
SmartMediaTM
GENERAL DESCRIPTION
The K9S1208V0M is a 64M(67,108,864)x8bit NAND Flash Memory with a spare 2,048K(2,097,152)x8bit. Its NAND cell provides the most cost-effective solution for the solid state mass storage market. A program operation programs the 528byte page in typically 200s and an erase operation can be performed in typically 2ms on a 16K-byte block. Data in the page can be read out at 50ns cycle time per byte. The I/O pins serve as the ports for address and data input/output as well as command inputs. The on-chip write controller automates all program and erase functions including pulse repetition, where required, and internal verify and margining of data. n, where required, and internal verify and margining of data. Even the write-intensive systems can take advantage of the K9S1208V0Ms extended reliability of 100K program/erase cycles by providing ECC(Error Correcting Code) with real time mapping-out algorithm. The K9S1208V0M is an optimum solution for large nonvolatile storage applications such as solid state file storage, digital voice recorder, digital still camera and other portable applications requiring non-volatility.
SmartMediaTM CARD(SSFDC)
PIN DESCRIPTION
Pin Name Pin Function Data Input/Outputs Command Latch Enable Address Latch Enable Chip Enable Read Enable Write Enable Write Protect Low Voltage Detect Ground Ready/Busy output Power Ground No Connection
22 VCC 21 CE 20 RE 19 R/B 18 GND 17 LVD 16 I/O7 15 I/O6 14 I/O5 13 I/O4 12 VCC
12
22
I/O0 ~ I/O7
1 2 3 4 5 VSS CLE ALE WE WP I/O0 I/O1 I/O2 I/O3
CLE ALE CE RE WE WP LVD GND R/B
11
1
6 7 8 9
ID 64MB
10 VSS 11 VSS
22 PAD SmartMediaTM
VCC VSS N.C
NOTE : Connect all VCC and VSS pins of each device to common power supply outputs. Do not leave VCC or VSS disconnected.
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K9S1208V0M-SSB0
Figure 1. FUNCTIONAL BLOCK DIAGRAM
VCC VSS A9 - A25 X-Buffers Latches & Decoders Y-Buffers Latches & Decoders
SmartMediaTM
512M + 16M Bit NAND Flash ARRAY
A0 - A7
(512 + 16)Byte x 131,072 Page Register & S/A
A8
Command Command Register
Y-Gating
I/O Buffers & Latches
VCC VSS I/0 0 I/0 7
CE RE WE
Control Logic & High Voltage Generator
Global Buffers
Output Driver
CLE ALE WP
Figure 2. ARRAY ORGANIZATION
1 Block = 32 Pages (16K + 512) Byte
128K Pages (=4,096 Blocks)
1st half Page Register (=256 Bytes)
2nd half Page Register (=256 Bytes)
1 Page = 528 Byte 1 Block = 528 Byte x 32 Pages = (16K + 512) Byte 1 Device = 528Byte x 32Pages x 4096 Blocks = 528 Mbits 8 bit 16 Byte
512B Byte
Page Register
512 Byte I/O 0 1st Cycle 2nd Cycle 3rd Cycle 4th Cycle A0 A9 A17 A25 I/O 1 A1 A10 A18 *L I/O 2 A2 A11 A19 *L 16 Byte I/O 3 A3 A12 A20 *L
I/O 0 ~ I/O 7
I/O 4 A4 A13 A21 *L
I/O 5 A5 A14 A22 *L
I/O 6 A6 A15 A23 *L
I/O 7 A7 A16 A24 *L Column Address Row Address (Page Address)
NOTE : Column Address : Starting Address of the Register. 00h Command(Read) : Defines the starting address of the 1st half of the register. 01h Command(Read) : Defines the starting address of the 2nd half of the register. * A8 is set to "Low" or "High" by the 00h or 01h Command. * L muxt be set to "Low".
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K9S1208V0M-SSB0
Product Introduction
SmartMediaTM
The K9S1208V0M is a 528Mbit(553,648,218 bit) memory organized as 131,072 rows(pages) by 528 columns. Spare sixteen columns are located from column address of 512 to 527. A 528-byte data register is connected to memory cell arrays accommodating data transfer between the I/O buffers and memory during page read and page program operations. The memory array is made up of 16 cells that are serially connected to form a NAND structure. Each of the 16 cells resides in a different page. A block consists of the 32 pages formed by two NAND structures, totaling 8,192 NAND structures of 16 cells. The array organization is shown in Figure 2. The program and read operations are executed on a page basis, while the erase operation is executed on a block basis. The memory array consists of 4,096 separately erasable 16K-byte blocks. It indicates that the bit by bit erase operation is prohibited on the K9S1208V0M. The K9S1208V0M has addresses multiplexed into 8 I/O's. This scheme dramatically reduces pin counts and allows systems upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written through I/O's by bringing WE to low while CE is low. Data is latched on the rising edge of WE. Command Latch Enable(CLE) and Address Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. The 64M byte physical space requires 26 addresses, thereby requiring four cycles for byte-level addressing: column address, low row address and high row address, in that order. Page Read and Page Program need the same four address cycles following the required command input. In Block Erase operation, however, only the three row address cycles are used. Device operations are selected by writing specific commands into the command register. Table 1 defines the specific commands of the K9S1208V0M. The device provides simultaneous program/erase capability up to four pages/blocks. By dividing the memory array into four 128Mbit separate planes, simultaneous multi-plane operation dramatically increases program/erase performance by 4X while still maintaining the conventional 512 byte structure. The extended pass/fail status for multi-plane program/erase allows system software to quickly identify the failing page/block out of selected multiple pages/blocks. Usage of multi-plane operations will be described further throughout this document.
Table 1. Command Sets
Function Read 1 Read 2 Read ID (1) Read ID (2) Reset Page Program (True) Page Program (Dummy) Page Program (Multi Block Program) Block Erase Multi-Plane Block Erase Read Status Read Multi-Plane Status 1st. Cycle 00h/01h 50h 90h 91h FFh 80h 80h 80h 60h 60h---60h 70h 71h
(2) (1)
2nd. Cycle 10h 11h 15h D0h D0h -
3rd. Cycle -
Acceptable Command
O
O O
NOTE : 1. The 00h command defines starting address of the 1st half of registers. The 01h command defines starting address of the 2nd half of registers. After data access on the 2nd half of register by the 01h command, the status pointer is automatically moved to the 1st half register(00h) on the next cycle.
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K9S1208V0M-SSB0
Memory Map
SmartMediaTM
The device is arranged in four 128Mbit memory planes. Each plane contains 1,024 blocks and 528 byte page registers. This allows it to perform simultaneous page program and block erase by selecting one page or block from each plane. The block address map is configured so that multi-plane program/erase operations can be executed for every four sequential blocks.
Figure 3. Memory Array Map
Plane 0 (1024 Block) Plane 1 (1024 Block) Plane 2 (1024 Block) Plane 3 (1024 Block)
Block 0 Page 0 Page 1
Block 1 Page 0 Page 1
Block 2 Page 0 Page 1
Block 3 Page 0 Page 1
Page 30 Page 31 Block 4 Page 0 Page 1
Page 30 Page 31 Block 5 Page 0 Page 1
Page 30 Page 31 Block 6 Page 0 Page 1
Page 30 Page 31 Block 7 Page 0 Page 1
Page 30 Page 31
Page 30 Page 31
Page 30 Page 31
Page 30 Page 31
Block 4088 Page 0 Page 1
Block 4089 Page 0 Page 1
Block 4090 Page 0 Page 1
Block 4091 Page 0 Page 1
Page 30 Page 31 Block 4092 Page 0 Page 1
Page 30 Page 31 Block 4093 Page 0 Page 1
Page 30 Page 31 Block 4094 Page 0 Page 1
Page 30 Page 31 Block 4095 Page 0 Page 1
Page 30 Page 31
Page 30 Page 31
Page 30 Page 31
Page 30 Page 31
528byte Page Registers
528byte Page Registers
528byte Page Registers
528byte Page Registers
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K9S1208V0M-SSB0
PIN DESCRIPTION
Command Latch Enable(CLE)
SmartMediaTM
The CLE input controls the path activation for commands sent to the command register. When active high, commands are latched into the command register through the I/O ports on the rising edge of the WE signal.
Address Latch Enable(ALE)
The ALE input controls the activating path for address to the internal address registers. Addresses are latched on the rising edge of WE with ALE high.
Chip Enable(CE)
The CE input is the device selection control. When CE goes high during a read operation the device is returned to standby mode. However, when the device is in the busy state during program or erase, CE high is ignored, and does not return the device to standby mode.
Write Enable(WE)
The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of the WE pulse. The WE must be held high when outputs are activated.
Read Enable(RE)
The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid tREA after the falling edge of RE which also increments the internal column address counter by one.
I/O Port : I/O 0 ~ I/O 7
The I/O pins are used to input command, address and data, and to output data during read operations. The I/O pins float to high-z when the chip is deselected or when the outputs are disabled.
Write Protect(WP)
The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage generator is reset when the WP pin is active low.
Ready/Busy(R/B)
The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or random read operation is in process and returns to high state upon completion. It is an open drain output and does not float to high-z condition when the chip is deselected or when outputs are disabled.
Low Voltage Detect(LVD)
The LVD is used to electrically detect the proper supply voltage. By connecting this pin to Vss through a pull-down resister, it is possible to distinguish 3.3V product from 5V product. When 3.3V is applied as Vcc to pins 12 and 22, a ' High'level can be detected on the system side if the device is a 3.3V product, and ' Low'level for 5V product.
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K9S1208V0M-SSB0
ABSOLUTE MAXIMUM RATINGS
Parameter Voltage on any pin relative to VSS Temperature Under Bias Storage Temperature Symbol VIN VCC TBIAS TSTG Rating -0.6 to + 4.6 -0.6 to + 4.6 -10 to +65 -20 to +65
SmartMediaTM
Unit V C C
NOTE : 1. Minimum DC voltage is -0.3V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns. Maximum DC voltage on input/output pins is VCC+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns. 2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED OPERATING CONDITIONS
(Voltage reference to GND, TA=0 to 55C)
Parameter Supply Voltage Supply Voltage Symbol VCC VSS Min 2.7 0 Typ. 3.3 0 Max 3.6 0 Unit V V
DC AND OPERATING CHARACTERISTICS(Recommended operating conditions otherwise noted.)
Parameter Operating Current Sequential Read Program Erase Stand-by Current(TTL) Stand-by Current(CMOS) Input Leakage Current Output Leakage Current Input High Voltage, All inputs Input Low Voltage, All inputs Output High Voltage Level Output Low Voltage Level Output Low Current(R/B) Symbol ICC1 ICC2 ICC3 ISB1 ISB2 ILI ILO VIH VIL VOH VOL IOL(R/B) IOH=-400A IOL=2.1mA VOL=0.4V Test Conditions tRC=50ns, CE=VIL, IOUT=0mA CE=VIH, WP=0V/VCC CE=VCC-0.2, WP=0V/VCC VIN=0 to 3.6V VOUT=0 to 3.6V Min 2.0 -0.3 2.4 8 Typ 10 10 10 10 10 Max 30 30 30 1 50 10 10 VCC+0.3 0.8 0.4 mA V A mA Unit
7
K9S1208V0M-SSB0
VALID BLOCK
Parameter Valid Block Number Symbol NVB Min 4026 Typ. -
SmartMediaTM
Max 4096 Unit Blocks
NOTE : 1. The K9S1208V0M may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not try to access these invalid blocks for program and erase. Refer to the attached technical notes for a appropriate management of invalid blocks. 2. Per the specification of the physical format version 1.2 by SSFDC forum, minimum 1,000 vaild blocks are guaranteed for each 16MB memory space.
AC TEST CONDITION
(TA=0 to 55C, VCC=2.7V~3.6V unless otherwise noted)
Parameter Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels Output Load (3.0V +/-10%) Output Load (3.3V +/-10%) Value 0.4V to 2.4V 5ns 1.5V 1 TTL GATE and CL=50pF 1 TTL GATE and CL=100pF
CAPACITANCE(TA=25C, VCC=3.3V, f=1.0MHz)
Item Input/Output Capacitance Input Capacitance Symbol CI/O CIN Test Condition VIL=0V VIN=0V Min Max 10 10 Unit pF pF
NOTE : Capacitance is periodically sampled and not 100% tested.
MODE SELECTION
CLE H L H L L L L X X X X ALE L H L H L L L X X X(1) X CE L L L L L L L X X X H H H X X X X H X X X X WE RE H H H H H WP X X H H H X X H H L 0V/VCC
(2)
Mode Read Mode Command Input Address Input(4clock) Write Mode Data Input sequential Read & Data Output During Read(Busy) During Program(Busy) During Erase(Busy) Write Protect Stand-by Command Input Address Input(4clock)
NOTE : 1. X can be VIL or VIH. 2. WP should be biased to CMOS high or CMOS low for standby.
Program / Erase Characteristics
Parameter Program Time Dummy Busy Time for Multi Plane Program Number of Partial Program Cycles in the Same Page Block Erase Time Main Array Spare Array Symbol tPROG tDBSY Nop tBERS Min Typ 200 1 2 Max 500 10 1 2 3 Unit s s cycle cycles ms
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K9S1208V0M-SSB0
AC Timing Characteristics for Command / Address / Data Input
Parameter CLE setup Time CLE Hold Time CE setup Time CE Hold Time WE Pulse Width ALE setup Time ALE Hold Time Data setup Time Data Hold Time Write Cycle Time WE High Hold Time Symbol tCLS tCLH tCS tCH tWP tALS tALH tDS tDH tWC tWH Min 0 10 0 10 25(1) 0 10 20 10 50 15
SmartMediaTM
Max Unit ns ns ns ns ns ns ns ns ns ns ns
NOTE : 1. If tCS is set less than 10ns, tWP must be minimum 35ns, otherwise, tWP may be minimum 25ns.
AC Characteristics for Operation
Parameter Data Transfer from Cell to Register ALE to RE Delay( ID read ) ALE to RE Delay(Read cycle) Ready to RE Low RE Pulse Width WE High to Busy Read Cycle Time RE Access Time RE High to Output Hi-Z CE High to Output Hi-Z RE High Hold Time Output Hi-Z to RE Low Last RE High to Busy(at sequential read) CE High to Ready(in case of interception by CE at read) CE High Hold Time(at the last serial read) (2) CE Access Time WE High to RE Low Device Resetting Time(Read/Program/Erase) Symbol tR tAR1 tAR2 tRR tRP tWB tRC tREA tRHZ tCHZ tREH tIR tRB tCRY tCEH tCEA tWHR tRST Min 10 50 20 30 50 15 15 0 100 60 Max 12 100 35 30 20 100 50 +tr(R/B) 45 5/10/500
(3) (1)
Unit s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s
NOTE : 1. The time to Ready depends on the value of the pull-up resistor tied R/B pin. 2. To break the sequential read cycle, CE must be held high for longer time than tCEH. 3. If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5us.
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K9S1208V0M-SSB0
SmartMedia Technical Notes
Invalid Block(s)
SmartMediaTM
Invalid blocks are defined as blocks that contain one or more invalid bits whose reliability is not guaranteed by Samsung. The information regarding the invalid block(s) is so called as the invalid block information. An invalid block(s) does not affect the performance of valid block(s) because it is isolated from the bit line and the common source line by a select transistor. The system design must be able to mask out the invalid block(s) via address mapping.
Identifying Invalid Block(s)
SSFDC Forum specifies the logical format and physical format to ensure compatibility of SmartMedia. Samsung pre-formats SmartMedia in the Forum-compliant format prior to shipping. Physical format standard by SSFDC Forum specifies that for the invalid blocks the 6th byte in the spare area (column address 517 for 4MB SmartMedia and higher densities, 261 for 2MB SmartMedia, respectively) contains two or more "0" bits to indicate a invalid block. Other than the blocks with format data and the invalid blocks are erased(FFh). Since the invalid block information is also erasable in most cases, it is impossible to recover the information once it has been erased. Therefore, the system must be able to recognize the invalid block(s) based on the original invalid block information and create the invalid block table via the following suggested flow chart(Figure 4). Any intentional erasure of the original invalid block information is prohibited.
Start
Set Block Address = 0
Increment Block Address
Create (or update) Invalid Block(s) Table
No
*
Check "FFh" ? Yes
Check "FFh" at the column address 517 (or 261) of the first page in the block
No
Last Block ?
Yes
End
Figure 4. Flow chart to create invalid block table.
10
K9S1208V0M-SSB0
SmartMedia Technical Notes (Continued)
Error in write or read operation
SmartMediaTM
Over its life time, the additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual data.The following possible failure modes should be considered to implement a highly reliable system. In the case of status read failure after erase or program, block replacement should be done. To improve the efficiency of memory space, it is recommended that the read or verification failure due to single bit error be reclaimed by ECC without any block replacement. The said additional block failure rate does not include those reclaimed blocks.
Failure Mode Erase Failure Write Program Failure Single Bit Failure
Detection and Countermeasure sequence Status Read after Erase --> Block Replacement Status Read after Program --> Block Replacement Read back ( Verify after Program) --> Block Replacement or ECC Correction Verify ECC -> ECC Correction
Read
ECC
: Error Correcting Code --> Hamming Code etc. Example) 1bit correction & 2bit detection
Program Flow Chart
If ECC is used, this verification operation is not needed. Start Write 00h
Write 80h
Write Address
Write Address
Write Data
Wait for tR Time
Write 10h
Verify Data
No
*
Program Error
Read Status Register
Yes Program Completed
I/O 6 = 1 ? or R/B = 1 ? Yes No I/O 0 = 0 ?
No
*
*
Program Error
: If program operation results in an error, map out the block including the page in error and copy the target data to another block.
Yes
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K9S1208V0M-SSB0
SmartMedia Technical Notes (Continued)
Erase Flow Chart
Start Write 60h Write Block Address Write D0h Read Status Register
SmartMediaTM
Read Flow Chart
Start Write 00h Write Address Read Data ECC Generation
I/O 6 = 1 ? or R/B = 1 ? Yes No I/O 0 = 0 ? Yes Erase Completed
No
Reclaim the Error
No
Verify ECC Yes Page Read Completed
*
Erase Error
*
: If erase operation results in an error, map out the failing block and replace it with another block.
Block Replacement
Buffer memory
error occurs Page a Block A When the error happens with page "a" of Block "A", try to write the data into another Block "B" from an external buffer. Then, prevent further system access to Block "A" (by creating a "invalid block" table or other appropriate scheme.)
Block B
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K9S1208V0M-SSB0
Pointer Operation of K9S1208V0M
SmartMediaTM
Samsung NAND Flash has three address pointer commands as a substitute for the two most significant column addresses. ' 00h' command sets the pointer to ' area(0~255byte), ' A' 01h'command sets the pointer to ' area(256~511byte), and ' B' 50h'command sets the pointer to ' area(512~527byte). With these commands, the starting column address can be set to any of a whole C' page(0~527byte). ' 00h' or ' 50h' is sustained until another address pointer command is inputted. ' 01h' command, however, is effective only for one operation. After any operation of Read, Program, Erase, Reset, Power_Up is executed once with ' 01h' command, the address pointer returns to ' area by itself. To program data starting from ' or ' area, ' A' A' C' 00h'or ' 50h'command must be inputted before ' 80h'command is written. A complete read operation prior to ' 80h' command is not necessary. To program data starting from ' area, ' B' 01h'command must be inputted right before ' 80h'command is written.
"A" area (00h plane)
"B" area (01h plane) 256 Byte
"C" area (50h plane) 16 Byte
Table 2. Destination of the pointer Command 00h 01h 50h Pointer position 0 ~ 255 byte 256 ~ 511 byte 512 ~ 527 byte Area 1st half array(A) 2nd half array(B) spare array(C)
256 Byte
"A"
"B"
"C" Internal Page Register
Pointer select commnad (00h, 01h, 50h)
Pointer
Figure 5. Block Diagram of Pointer Operation
(1) Command input sequence for programming ' area A'
The address pointer is set to ' area(0~255), and sustained A' Address / Data input 00h 80h 10h 00h 80h Address / Data input 10h
' ,' ,' area can be programmed. A' B' C' It depends on how many data are inputted.
' 00h'command can be omitted.
(2) Command input sequence for programming ' area B'
The address pointer is set to ' area(256~512), and will be reset to B' ' area after every program operation is executed. A' Address / Data input 01h 80h 10h 01h 80h Address / Data input 10h
' , ' area can be programmed. B' C' It depends on how many data are inputted.
' 01h'command must be rewritten before every program operation
(3) Command input sequence for programming ' area C'
The address pointer is set to ' area(512~527), and sustained C' Address / Data input 50h 80h 10h 50h 80h Address / Data input 10h
Only ' area can be programmed. C'
' 50h'command can be omitted.
13
K9S1208V0M-SSB0
System Interface Using CE don' t-care.
SmartMediaTM
For an easier system interface, CE may be inactive during the data-loading or sequential data-reading as shown below. The internal 528byte page registers are utilized as seperate buffers for this operation and the system design gets more flexible. In addition, for voice or audio applications which use slow cycle time on the order of u-seconds, de-activating CE during the data-loading and reading would provide significant savings in power consumption.
t-care. Figure 6. Program Operation with CE don' CLE
CE don' t-care
CE
WE ALE
I/O0~7
80h
Start Add.(4Cycle)
Data Input
Data Input
10h
tCS CE
tCH CE
tCEA
tREA tWP WE I/O0~7 out RE
Figure 7. Read Operation with CE don' t-care.
CLE
CE don' t-care Must be held low during tR.
CE
RE ALE R/B tR
WE
I/O0~7
00h
Start Add.(4Cycle)
Data Output(sequential)
14
K9S1208V0M-SSB0
* Command Latch Cycle
SmartMediaTM
CLE tCLS tCS CE tCLH tCH
tWP WE
tALS ALE tDS I/O0~7
tALH
tDH
Command
* Address Latch Cycle
tCLS CLE
tCS CE
tWC
tWC
tWC
tWP WE tALS ALE tDS I/O0~7 tDH tWH tALH tALS
tWP tWH tALH tALS
tWP tWH tALH tALS
tWP tALH
tDS
tDH
tDS
tDH
tDS
tDH
A0~A7
A9~A16
A17~A24
A25
15
K9S1208V0M-SSB0
* Input Data Latch Cycle
tCLH CLE
SmartMediaTM
tCH CE
tALS ALE
tWC
tWP WE tDS I/O0~7 tWH tDH
tWP
tDH
tWP tDH
tDS
tDS
DIN 0 DIN 1 DIN 511
* Sequential Out Cycle after Read(CLE=L, WE=H, ALE=L)
tREH RE tRHZ*
CE
tRC tCHZ*
tREA
tREA
tREA
tRHZ* I/O0~7 tRR R/B Dout Dout
Dout
NOTES : Transition is measured 200mV from steady state voltage with load. This parameter is sampled and not 100% tested.
16
K9S1208V0M-SSB0
* Status Read Cycle
tCLS CLE tCLS tCS CE tCH tWP WE tWHR RE tDS I/O0~7 70h tDH tIR tREA tCEA tCLH
SmartMediaTM
tCHZ*
tRHZ* Status Output
READ1 OPERATION(READ ONE PAGE)
CLE tCEH CE tWC WE tWB tAR2 ALE tR RE tRR I/O0~7
00h or 01h A0 ~ A7 A9 ~ A16 A17 ~ A24 A25 Dout N Dout N+1 Dout N+2
tCHZ
tCRY
tRC
tRHZ
Dout 527
Column Address
Page(Row) Address Busy
tRB
R/B
17
K9S1208V0M-SSB0
READ1 OPERATION (INTERCEPTED BY CE)
SmartMediaTM
CLE
CE
WE tWB tAR2 ALE tR RE tRR I/O0~7
00h or 01h
tCHZ
tRC
A0 ~ A7
A9 ~ A16
A17 ~ A24
A25
Dout N
Dout N+1
Dout N+2
Column Address
Page(Row) Address Busy
R/B
READ2 OPERATION(READ ONE PAGE)
CLE
CE
WE tWB ALE
tR tAR2 tRR
RE
I/O0~7
50h
A0 ~ A7
A9 ~ A16 A17 ~ A24
A25
Dout 511+M
Dout 527
R/B M Address
A0~A3 : Valid Address A4~A7 : Dont care
Selected Row
512
16 Start address M
18
K9S1208V0M-SSB0
SEQUENTIAL ROW READ OPERATION ( WITHIN A BLOCK )
CLE
SmartMediaTM
CE
WE
ALE
RE
I/O0~7
00h
A0 ~ A7 A9 ~ A16 A17 ~ A24
A25
Dout N
Dout N+1
Dout 527
Dout 0
Dout 1

Dout 527
Ready R/B
M
Busy
Busy
M+1
N
Output
Output
PAGE PROGRAM OPERATION
CLE
CE
WE tWB ALE tPROG
RE
Din Din 10h N 527 1 up to 528 Byte Data Program Command Serial Input
I/O0~7
80h
A0 ~ A7 A9 ~ A16 A17 ~ A24 Page(Row) Address
A25
tWC
tWC
tWC
70h Read Status Command
I/O0
Sequential Data Column Input Command Address
R/B
I/O0=0 Successful Program I/O0=1 Error in Program
19
K9S1208V0M-SSB0
BLOCK ERASE OPERATION(ERASE ONE BLOCK)
SmartMediaTM
CLE
CE tWC WE tWB ALE tBERS
RE
I/O0~7
60h
A9 ~ A16 A17 ~ A24 Page(Row) Address
A25
DOh
70h
I/O 0
R/B
Auto Block Erase Setup Command Erase Command
Busy
Read Status Command
I/O0=0 Successful Erase I/O0=1 Error in Erase
20
Multi-Plane Page Program Operation
CLE
CE
tWC
K9S1208V0M-SSB0
WE
tWB tDBSY tWB tPROG
ALE
RE
I/O0~7
A25 80h A0 ~ A7 A9 ~ A16 A17 ~ A24 A25 11h Program 1 up to 528 Byte Data Command (Dummy) Serial Input
Max. three times repeatable
Last Plane Input & Program
tDBSY :
typ. 1us max. 10us
Ex.) Four-Plane Page Program tDBSY tDBSY tDBSY tPROG
R/B
21
Address & Data Input 11h 80h A0 ~ A7 & A9 ~ A25 528 Byte Data Address & Data Input A0 ~ A7 & A9 ~ A25 528 Byte Data 11h 80h Address & Data Input A0 ~ A7 & A9 ~ A25 528 Byte Data 11h
80h
A0 ~ A7 A9 ~ A16 A17 ~ A24
Din N
Din 527
Din N
Din 527
71h 10h Program Confirm Command (True)
I/O
Sequential Data Input Command
Column Address
Page(Row) Address
Read Multi-Plane Status Command
R/B
I/O0~7
80h
80h
Address & Data Input A0 ~ A7 & A9 ~ A25 528 Byte Data
SmartMediaTM
10h
71h
K9S1208V0M-SSB0
Multi-Plane Block Erase Operation
SmartMediaTM
CLE
CE tWC WE tWB ALE tBERS
RE
I/O0~7
60h
A9 ~ A16 A17 ~ A24 Page(Row) Address
A25
DOh
71h
I/O 0
Block Erase Setup Command
Erase Confirm Command Read Multi-Plane Status Command
Max. 4 times repeatable
* For Multi-Plane Erase operation, Block address to be erased should be repeated before "D0H" command.
Ex.) Four-Plane Block Erase Operation R/B I/O0~7
Address Address 60h Address D0h
R/B
Busy
tBERS
71h
60h
Address A9 ~ A25
60h
60h
22
K9S1208V0M-SSB0
Read ID (1) Operation
CLE CE
SmartMediaTM
WE ALE
RE tREA I/O 0 ~ 7
90h Read ID (1) Command 00h Address. 1cycle ECh 76h
Maker Code Device Code
Read ID (2) Operation
CLE CE
WE ALE
RE tREA I/O 0 ~ 7
91h Read ID (2) Command 00h Address. 1cycle 20h Maker Code
ID Defintition Table 90 ID : Access command = 90H
READ ID (1) 1 Byte 2nd Byte
st
91 ID : Access command = 91H
READ ID (2) 1 Byte
st
Value ECh 76h
Description Maker Code Device Code
Value 20h
Description Supports Multi Plane Operation
23
K9S1208V0M-SSB0
Device Operation
PAGE READ
SmartMediaTM
Upon initial device power up, the device defaults to Read1 mode. This operation is also initiated by writing 00h to the command register along with four address cycles. Once the command is latched, it does not need to be written for the following page read operation. Three types of operations are available : random read, serial page read and sequential row read. The random read mode is enabled when the page address is changed. The 528 bytes of data within the selected page are transferred to the data registers in less than 12s(tR). The system controller can detect the completion of this data transfer(tR) by analyzing the output of R/B pin. Once the data in a page is loaded into the registers, they may be read out in 50ns cycle time by sequentially pulsing RE. High to low transitions of the RE clock output the data stating from the selected column address up to the last column address. After the data of last column address is clocked out, the next page is automatically selected for sequential row read. Waiting 12s again allows reading the selected page. The sequential row read operation is terminated by bringing CE high. The way the Read1 and Read2 commands work is like a pointer set to either the main area or the spare area. The spare area of bytes 512 to 527 may be selectively accessed by writing the Read2 command. Addresses A0 to A3 set the starting address of the spare area while addresses A4 to A7 are ignored. Unless the operation is aborted, the page address is automatically incremented for sequential row read as in Read1 operation and spare sixteen bytes of each page may be sequentially read. The Read1 command(00h/01h) is needed to move the pointer back to the main area. Figures 8 to 11 show typical sequence and timings for each read operation.
Figure 8. Read1 Operation CLE CE WE ALE tR R/B RE I/O0~7
00h Start Add.(4Cycle) A0 ~ A7 & A9 ~ A25 Data Output(Sequential)
(00h Command) 1st half array 2st half array
(01h Command)* 1st half array 2st half array
Data Field
Spare Field
Data Field
Spare Field
* After data access on 2nd half array by 01h command, the start pointer is automatically moved to 1st half array (00h) at next cycle.
24
K9S1208V0M-SSB0
Figure 9. Read2 Operation CLE CE WE ALE R/B RE I/O0~7
50h Start Add.(4Cycle) A0 ~ A3 & A9 ~ A25 (A4 ~ A7 : Dont Care)
1st half array 2nd half array
SmartMediaTM
tR
Data Output(Sequential) Spare Field
Data Field
Spare Field
Figure 10. Sequential Row Read1 Operation tR tR
R/B I/O0 ~ 7
Start Add.(4Cycle) A0 ~ A7 & A9 ~ A25 (00h Command)
1st half array
tR
00h 01h
Data Output 1st
Data Output 2nd (528 Byte) (01h Command)
1st half array 2nd half array
Data Output Nth (528 Byte)
2nd half array
1st 2nd Nth
Block
1st 2nd Nth
Data Field
Spare Field
Data Field
Spare Field
The Sequential Read 1 and 2 operation is allowed only within a block and after the last page of a block is readout, the sequential read operation must be terminated by bringing CE high. When the page address moves onto the next block, read command and address must be given.
25
K9S1208V0M-SSB0
Figure 11. Sequential Row Read2 Operation tR tR
SmartMediaTM
R/B I/O0~7
tR
50h
Start Add.(4Cycle) A0 ~ A3 & A9 ~ A25 (A4 ~ A7 : Dont Care)
Data Output 1st
Data Output 2nd (16Byte)
Data Output Nth (16Byte)
1st Block Nth
Data Field
Spare Field
PAGE PROGRAM
The device is programmed basically on a page basis, but it does allow multiple partial page programing of a byte or consecutive bytes up to 528, in a single page program cycle. The number of consecutive partial page programming operation within the same page without an intervening erase operation must not exceed 1 for main array and 2 for spare array. The addressing may be done in any random order in a block. A page program cycle consists of a serial data loading period in which up to 528 bytes of data may be loaded into the page register, followed by a non-volatile programming period where the loaded data is programmed into the appropriate cell. Serial data loading can be started from 2nd half array by moving pointer. About the pointer operation, please refer to the attached technical notes. The serial data loading period begins by inputting the Serial Data Input command(80h), followed by the four cycle address input and then serial data loading. The bytes other than those to be programmed do not need to be loaded.The Page Program confirm command(10h) initiates the programming process. Writing 10h alone without previously entering the serial data will not initiate the programming process. The internal write state control automatically executes the algorithms and timings necessary for program and verify, thereby freeing the system controller for other tasks. Once the program process starts, the Read Status Register command may be entered, with RE and CE low, to read the status register. The system controller can detect the completion of a program cycle by monitoring the R/B output, or the Status bit(I/O 6) of the Status Register. Only the Read Status command and Reset command are valid while programming is in progress. When the Page Program is complete, the Write Status Bit(I/O 0) may be checked(Figure 12). The internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. The command register remains in Read Status command mode until another valid command is written to the command register.
Figure 12. Program & Read Status Operation tPROG R/B I/O0~7
80h
Address & Data Input A0 ~ A7 & A9 ~ A25 528 Byte Data
10h
70h
I/O0
Pass
Fail
26
K9S1208V0M-SSB0
BLOCK ERASE
SmartMediaTM
The Erase operation is done on a block(16K Byte) basis. Block address loading is accomplished in three cycles initiated by an Erase Setup command(60h). Only address A14 to A25 is valid while A9 to A13 is ignored. The Erase Confirm command(D0h) following the block address loading initiates the internal erasing process. This two-step sequence of setup followed by execution command ensures that memory contents are not accidentally erased due to external noise conditions. At the rising edge of WE after the erase confirm command input, the internal write controller handles erase and erase-verify. When the erase operation is completed, the Write Status Bit(I/O 0) may be checked. Figure 13 details the sequence.
Figure 13. Block Erase Operation tBERS
R/B I/O0~7
60h
Address Input(3Cycle) Block Add. : A9 ~ A25
D0h
70h
I/O0 Fail Fail
Pass
MULTI-PLANE PAGE PROGRAM
Multi-Plane Page Program is an extension of Page Program, which is executed for a single plane with 528 byte page registers. Since the device is equipped with four memory planes, activating the four sets of 528 byte page registers enables a simultaneous programming of four pages. Partial activation of four planes is also permitted. After writing the first set of data up to 528 byte into the selected page register, Dummy Page Program command (11h) instead of actual Page Program (10h) is inputted to finish data-loading of the current plane and move to the next plane. Since no programming process is involved, R/B remains in Busy state for a short period of time(tDBSY). Read Status command (standard 70h or alternate 71h) may be issued to find out when the device returns to Ready state by polling the Ready/Busy status bit(I/O 6). Then the next set of data for one of the other planes is inputted with the same command and address sequences. After inputting data for the last plane, actual True Page Program (10h) instead of dumy Page Program command (11h) must be followed to start the programming process. The operation of R/B and Read Status is the same as that of Page Program. Since maximum four pages are programmed simultaneously, pass/fail status is available for each page when the program operation completes. The extended status bits (I/O1 through I/ O 4) are checked by inputting the Read Multi-Plane Status Register. Status bit of I/O 0 is set to "1" when any of the pages fails. MultiPlane page Program with "01h" pointer is not supported, thus prohibited.
Figure 14. Four-Plane Page Program R/B I/O0~7 tDBSY tDBSY tDBSY tPROG
80h
Address & 11h Data Input A0 ~ A7 & A9 ~ A25 528 Byte Data
80h
Address & Data Input
11h
80h
Address & Data Input
11h
80h
Address & Data Input
10h
71h
80h
11h
80h
11h
80h
11h
80h
10h
Data input
Plane 0 (1024 Block) Plane 1 (1024 Block) Plane 2 (1024 Block) Plane 3 (1024 Block)
Block 0 Block 4
Block 1 Block 5
Block 2 Block 6
Block 3 Block 7
Block 4088 Block 4092
Block 4089 Block 4093
Block 4090 Block 4094
Block 4091 Block 4095
27
K9S1208V0M-SSB0
RESTRICTION IN ADDRESSING WITH PLANE-PLANE PAGE PROGRAM
SmartMediaTM
While any block in each plane may be addressable for Multi-Plane Page Program, the four least significant addresses(A9-A13) for the selected pages at one operation must be the same. Figure 15 shows an example where 2nd page of each addressed block is selected for four planes. However, any arbitrary sequence is allowed in addressing multiple planes as shown in Figure16.
Figure 15. Multi-Plane Program & Read Status Operation
Plane 0 (1024 Block) Plane 1 (1024 Block) Plane 2 (1024 Block) Plane 3 (1024 Block)
Block 0 Page 0 Page 1
Block 1 Page 0 Page 1
Block 2 Page 0 Page 1
Block 3 Page 0 Page 1
Page 30 Page 31
Page 30 Page 31
Page 30 Page 31
Page 30 Page 31
Figure 16. Addressing Multiple Planes
80h Plane 2 11h 80h Plane 0 11h 80h Plane3 11h 80h Plane 1 10h
Figure 17. Multi-Plane Page Program & Read Status Operation tPROG R/B I/O0~7
Last Plane input
80h
Address & Data Input A0 ~ A7 & A9 ~ A25 528 Byte Data
10h
71h
I/O
Pass
Fail
The 15h command may be used as actual Page Program with 10h command. The pass/fail status data with 15h command are accumulated until the programming with 10h command as shown in Figure 18. Note that program with 10h command should be executed for the last pages of each four multi-plane blocks. Figure 18 shows an example when the 2nd page of plane 1 fails during multi-plane page program and fail status("1") sets.
Figure 18. Multi-Plane Page Program Using 15h Command
Read Status Register Data by 71h Command Plane 0 1st Page 2nd Page Block N 31th Page 32nd Page
80h 11h 80h 11h 80h 11h 80h 15h 80h 11h 80h
Plane 1
11h 80h
Plane 2
11h 80h
Plane 3
15h
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 0 1 0 0 0 1 0 0 0 0 X X 1 1 0 0
80h
11h
80h
11h
80h
11h
80h
15h
"Fail"
1 1
0 0
1 1
0 0
0 0
X X
1 1
0 0
80h
11h
80h
11h
80h
11h
80h
10h
1st Page Block N+1
80h
11h
80h
11h
80h
11h
80h
15h
0
0
0
0
0
X
1
0
- Please refer to "Read Status Register Definition" of Table 2 on page 29. - X means "don' cared". t
28
K9S1208V0M-SSB0
MULTI-PLANE BLOCK ERASE
SmartMediaTM
Basic concept of Multi-Plane Block Erase operation is identical to that of Multi-Plane Page Program. Up to four blocks, one from each plane can be simultaneously erased. Standard Block Erase command sequences (Block Erase Setup command followed by three address cycles) may be repeated up to four times for erasing up to four blocks. Only one block should be selected from each plane. The Erase Confirm command initiates the actual erasing process. The completion is detected by analyzing R/B pin or Ready/Busy status (I/O 6). Upon the erase completion, pass/fail status of each block is examined by reading extended pass/fail status(I/O 1 through I/O 4).
Figure 19. Four Block Erase Operation R/B I/O0~7
Address (3 Cycle) Address (3 Cycle) Address (3 Cycle) 60h Address (3 Cycle) D0h
tBERS
71h
60h
60h
60h
I/O
Pass
A0 ~ A7 & A9 ~ A25 Fail
READ STATUS
The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether the program or erase operation is completed successfully. After writing 70h command to the command register, a read cycle outputs the content of the Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or CE does not need to be toggled for updated status. Refer to table 2 for specific Status Register definitions. The command register remains in Status Read mode until further commands are issued to it. Therefore, if the status register is read during a random read cycle, a read command(00h or 50h) should be given before sequential page read cycle. For Read Status of Multi Plane Program/Erase, the Read Multi-Plane Status command(71h) should be used to find out whether multi-plane program or erase operation is completed, and whether the program or erase operation is completed successfully. The pass/fail status data must be checked only in the Ready condition after the completion of Multi-Plane program or erase operation.
Table2. Read Staus Register Definition
I/O No. I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 Status Total Pass/Fail Plane 0 Pass/Fail Plane 1 Pass/Fail Plane 2 Pass/Fail Plane 3 Pass/Fail Reserved Device Operation Write Protect Definition by 70h Command Pass : "0" Must be don' -cared t Must be don' -cared t Must be don' -cared t Must be don' -cared t Must be don' -cared t Busy : "0" Protected : "0" Ready : "1" Not Protected : "1" Fail : "1" Definition by 71h Command Pass : "0"(1) Pass : "0"
(2)
Fail : "1" Fail : "1" Fail : "1" Fail : "1" Fail : "1"
Pass : "0"(2) Pass : "0" Pass : "0"
(2) (2)
Must be don' t-cared Busy : "0" Protected : "0" Ready : "1" Not Protected : "1"
NOTE : 1. I/O 0 describes combined Pass/Fail condition for all planes. If any of the selected multiple pages/blocks fails in Program/
Erase operation, it sets "Fail" flag. 2. The pass/fail status applies only to the corresponding plane.
29
K9S1208V0M-SSB0
READ ID
SmartMediaTM
The device contains a product identification mode, initiated by writing 90h and 91h to the command register, followed by an address input of 00h. Two read cycles with 90h sequentially output the manufacture code(ECh) and the device code (76h) respectively. One read cycle with 91h outputs the Multi plane operation code(20h). 20h means that device supports Multi Plane operation. The command register remains in Read ID mode until further commands are issued to it. Figure 20 and 21 show the operation sequence.
Figure 20. Read ID (1) Operation CLE tCEA CE WE tAR1 ALE tWHR RE I/O0~7 tREA
00h Address. 1cycle ECh Maker code
90h
76h Device code
Figure 21. Read ID (2) Operation
CLE tCEA CE WE tAR1 ALE tWHR RE I/O0~7 tREA
00h Address. 1cycle 20h Maker code
91h
30
K9S1208V0M-SSB0
RESET
SmartMediaTM
The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no longer valid, as the data will be partially programmed or erased. The command register is cleared to wait for the next command, and the Status Register is cleared to value C0h when WP is high. Refer to table 4 for device status after reset operation. If the device is already in reset state a new reset command will not be accepted by the command register. The R/B pin transitions to low for tRST after the Reset command is written. Reset command is not necessary for normal operation. Refer to Figure 22 below.
Figure 22. RESET Operation tRST R/B I/O0~7
FFh
Table4. Device Status
After Power-up Operation Mode Read 1 After Reset Waiting for next command
READY/BUSY
The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random read completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command register or random read is started after address loading. It returns to high when the internal controller has finished the operation. The pin is an open-drain driver thereby allowing two or more R/B outputs to be Or-tied. An appropriate pull-up resister is required for proper operation and the value may be calculated by the following equation.
Rp VCC VCC(Max.) - VOL(Max.) Rp = R/B open drain output IOL + IL = 3.2V 8mA + IL
where IL is the sum of the input currents of all devices tied to the R/B pin.
GND Device
31
K9S1208V0M-SSB0
DATA PROTECTION
SmartMediaTM
The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector disables all functions whenever Vcc is below about 2V. WP pin provides hardware protection and is recommended to be kept at VIL during power-up and power-down as shown in Figure 23. The two step command sequence for program/erase provides additional software protection.
Figure 23. AC Waveforms for Power Transition
~ 2.5V
~ 2.5V
VCC
WP
32
High
SmartMedia Dimensions
DIMENSIONS
22 PAD SOLID STATE FLOPPY DISK CARD (3.3V) SOLID STATE PRODUCT OUTLINE
SmartMediaTM
Unit:mm
37.00.1 5.00.2
0.150.05
Index Label Area 10.00.2 Write Protect Area Contact Area (+0.1mm package body surface) 33.00.2 45.00.1 27.5 22.1(Max)
4.5(Min)
0.5mm Chamfer 4.2(Min) (3.3V Card)
8.650 7.900 6.500
0.000
0 5.
1.50.1 27.0
0.760.08
2.140 TYP 0.400 TYP
12
12.700 11
10.160
7.620
5.080
2.540
0.000
22
I/O4
I/O5
I/O6
I/O7
vcc
GND
R/B
RE
CE
vcc vSS
vcc
CLE
I/O3
I/O2
I/O1 33
I/O0
0.000
ALE
vSS
WP
2.540
WE
5.080
6.500 7.900 8.650 1
10.160
12.700
7.620

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